This invention relates to a programmable function block, which is a logic building unit in a logic device that can implement a various functions depending on user programs.
In recent years, the logic devices such as programmable logic devices (PLDs), field programmable gate arrays (FPGAs) or the like have been developing rapidly. By improving of integration density and speed, use of the logic devices has been elaborated not only to emulation on designing of application specific integrated circuits (ASICs) and replacing of simple peripheral circuits, but also to a reconfigurable computer which is able to change hardware configuration in accordance with applications.
In order to implement a wide variety of logic functions, combined multiplexer circuits or look-up tables (LUT) are used in the programmable function blocks of the conventional PLDs or FPGAs. As a result, the PLDs or FPGAs is disadvantageous in that performance diminishes in arithmetic operations, which are frequently used in the computer.
On the other hand, an arithmetic and logic unit (ALU) comprising a full adder as a main component, that is used in general-purpose processors up to now, is superior in performance of arithmetic operation. However, the ALU is not suitable to use as the programmable function block for PLDs or FPGAS. This is because the ALU has a poor function to use as a logic circuit.
In order to overcome the above-mentioned problems, another programmable function block is proposed in the manner which will later be described in conjunction with FIG. 1 (U.S. patent application Ser. No. 09/169,948). The prior art programmable function block acquires high functionality by adding a pre-logic circuit having a rich logic function to a full adder.
However, two problems still remain in the prior art programmable function block. A first problem is a large delay. A second problem is a large occupied area.